ASIC Design Methodology for 3D NOC Based Heterogeneous Multi Processor on Chip
The number of cores increases every 18 months following an exponential curve. The NoC has been considered as an emerging solution to deal with the problem of the chip interconnects, but the use of the Nanometer technology has presented a new major limitation where the interconnect delay overcomes the gate delay. 3D IC was one of the proposed solutions to deal with this problem. Even though there are some industrial and academic 3D tools, the shortage of a complete 3D dedicated workflow represents the major challenge in this field. We presented in this work a state of the art of the existing 2D and 3D workflow methodologies. New 2D and 3D NoC synthesis workflows were also proposed.
The optimization of the proposed design has been performed with modeFRONTIER. During this step of design, the shortage of information about the choice of the suitable machines, tools, platforms, number of licences was a real handicap. That is why we performed a Design Space Exploration by changing the different options of the processors and the NoC. We applied the NSGA-II algorithm in order to find the optimized sets of individuals which are minimizing the area and the execution time of the design. During our workflow implementation, three basic tools were used which are FlexNoC (NoC extraction), EDK (place and route), zCui (portioning and execution). We performed a Design Space Exploration in order to study the effect of the different parameters on the performance of those tools. Thanks to the variation of the machines, the population size, the number of FPGA and the architecture of the MPSOC, we provide a wide data base which can be the input of a predictive mathematical model. Thanks to this model the user can have a better idea to make different choices during the implementation of his design.